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asahi kasei [AK5381] ms0200-e-01 2004/04 - 1 - general description the AK5381 is a stereo a/d converter with wide sampling rate of 4khz 96khz and is suitable for high-end audio system. the AK5381 achieves high accuracy and low cost by using enhanced dual bit ? techniques. the AK5381 requires no external components because the analog inputs are single-ended. the audio interface has two formats (msb justified, i 2 s) and can correspond to many systems like music instrument and av receiver. features ? stereo ? adc ? on-chip digital anti-alias filtering ? single-ended input ? digital hpf for dc-offset cancel ? s/(n+d): 96db@5v for 48khz ? dr: 106db@5v for 48khz ? s/n: 106db@5v for 48khz ? sampling rate ranging from 4khz to 96khz ? master clock: 256fs/384fs/512fs/768fs ( 48khz) 256fs/384fs ( 96khz) ? audio interface: master or slave mode selectable ? input level: ttl/cmos selectable AK5381 does not support ttl level mode at fs=48khz to 96khz. ? output format: 24bit msb justified / i 2 s selectable ? power supply: 4.5 5.5v (va) 2.7 5.5v (vd at 48khz) 3.0 5.5v (vd at 96khz) ? ta = -40 85 c ? small 16pin tssop package ? ak5380 pin-compatible ? modulator mclk ainl lrck sclk sdto dif vcom clock divider ainr agnd v a decimation filter serial i/o interface voltage reference cks1 dgnd vd cks2 ? modulator decimation filter pdn cks0 24bit 96khz ? adc AK5381
asahi kasei [AK5381] ms0200-e-01 2004/04 - 2 - ? ordering guide AK5381vt ? 40 +85 c 16pin tssop (0.65mm pitch) akd5381 evaluation board for AK5381 ? pin layout cks1 vcom vd dgnd ainr ainl agnd va top view 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 dif pdn lrck mclk sclk cks2 cks0 sdto ? compatibility with ak5380 ak5380 AK5381 master mode not available available hpf off not available available ttl level mode 4khz to 96khz 4khz to 48khz vih@ttl level mode 2.2v 2.4v vd (digital supply) 4.5 to 5.5v@fs=96khz 3.0 to 5.5v@fs=96khz pin #3 nc cks1 pin #15 ttl cks2 pin #16 tst cks0
asahi kasei [AK5381] ms0200-e-01 2004/04 - 3 - pin / function no. pin name i/o function 1 ainr i rch analog input pin 2 ainl i lch analog input pin 3 cks1 i mode select 1 pin 4 vcom o common voltage output pin, va/2 bias voltage of adc input. 5 agnd - analog ground pin 6 va - analog power supply pin, 4.5 5.5v 7 vd - digital power supply pin, 2.7 5.5v(fs=4k 48khz), 3.0 5.5v(fs=48k 96khz) 8 dgnd - digital ground pin 9 sdto o audio serial data output pin ?l? output at power-down mode. 10 lrck i/o output channel clock pin ?l? output in master mode at power-down mode. 11 mclk i master clock input pin 12 sclk i/o audio serial data clock pin ?l? output in master mode at power-down mode. 13 pdn i power down mode pin ?h?: power up, ?l?: power down 14 dif i audio interface format pin ?h? : 24bit i 2 s compatible, ?l? : 24bit msb justified 15 cks2 i mode select 2 pin 16 cks0 i mode select 0 pin note: all digital input pins should not be left floating.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 4 - absolute maximum ratings (agnd, dgnd=0v; note 1) parameter symbol min max units power supplies: analog digital |agnd ? dgnd| (note 2) va vd ? gnd ? 0.3 ? 0.3 - 6.0 6.0 0.3 v v v input current, any pin except supplies iin - 10 ma analog input voltage (ainl, ainr, cks1 pins) vina ? 0.3 va+0.3 v digital input voltage (all digital input pins except cks1 pin) vind ? 0.3 vd+0.3 v ambient temperature (powered applied) ta ? 40 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. agnd and dgnd must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital (fs=4khz to 48khz) digital (fs=48khz to 96khz) va vd vd 4.5 2.7 3.0 5.0 5.0 5.0 5.5 va va v v v note 1. all voltages with respect to ground. note 3. the power up sequence between va and vd is not critical. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 5 - analog characteristics (ta=25 c; va=vd=5.0v; agnd=dgnd=0v; fs=48khz, 96khz; sclk=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz, 40hz 40khz at fs=96khz; unless otherwise specified) parameter min typ max units adc analog input characteristics: resolution 24 bits input voltage (note 4) 2.7 3.0 3.3 vpp s/(n+d) ( ? 1dbfs) fs=48khz fs=96khz 88 82 96 90 db db dr ( ? 60dbfs) fs=48khz, a-weighted fs=96khz 100 94 106 102 db db s/n fs=48khz, a-weighted fs=96khz 100 94 106 102 db db input resistance fs=48khz fs=96khz 10 6 15 9 k ? k ? interchannel isolation 90 110 db interchannel gain mismatch 0.1 0.5 db gain drift 100 150 ppm/ c power supply rejection (note 5) 50 - db power supplies power supply current normal operation (pdn pin = ?h?) va vd (fs=48khz) vd (fs=96khz) power down mode (pdn pin = ?l?) (note 6) va+vd 16 8 14 10 24 12 21 100 ma ma ma a note 4. this value is the full scale (0db) of the input voltage. input voltage is proportional to va voltage. vin = 0.6 x va (vpp). note 5. psr is applied to va and vd with 1khz, 50mvpp. note 6. all digital input pins are held vd or dgnd.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 6 - filter characteristics (fs=48khz) (ta= ? 40 85 c; va=4.5 5.5v; vd=2.7 5.5v) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 7) 0.005db 0.02db ? 0.06db ? 6.0db pb 0 - - - 21.768 22.0 24.0 21.5 - - - khz khz khz khz stopband sb 26.5 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay distortion ? gd 0 s group delay (note 8) gd 27.6 1/fs adc digital filter (hpf): frequency response (note 7) ? 3db ? 0.5db ? 0.1db fr 1.0 2.9 6.5 hz hz hz filter characteristics (fs=96khz) (ta= ? 40 85 c; va=4.5 5.5v; vd=3.0 5.5v) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 7) 0.005db 0.02db ? 0.06db ? 6.0db pb 0 - - - 43.536 44.0 48.0 43.0 - - - khz khz khz khz stopband sb 53.0 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay distortion ? gd 0 s group delay (note 8) gd 27.6 1/fs adc digital filter (hpf): frequency response (note 7) ? 3db ? 0.5db ? 0.1db fr 2.0 5.8 13.0 hz hz hz note 7. the passband and stopband frequencies scale with fs . the reference frequency of these responses is 1khz. note 8. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 7 - dc characteristics (cmos level mode) (ta= ? 40 85 c; va=4.5 5.5v; vd=2.7 5.5v@fs=4khz 48khz, vd=3.0 5.5v@fs= 96khz) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vd - - - - 30%vd v v high-level output voltage (iout= ? 100 a) low-level output voltage (iout=100 a) voh vol vd-0.5 - - - - 0.5 v v input leakage current iin - - 10 a dc characteristics (ttl level mode) (ta= ? 40 85 c; va=4.5 5.5v; vd=4.5 5.5v@fs=4khz 48khz) parameter symbol min typ max units high-level input voltage (cks2-0 pins) (all pins except cks2-0 pins) low-level input voltage (cks2-0 pins) (all pins except cks2-0 pins) vih vih vil vil 70%vd 2.4 - - - - - - - - 30%vd 0.8 v v v v high-level output voltage (iout= ? 100 a) low-level output voltage (iout=100 a) voh vol vd-0.5 - - - - 0.5 v v input leakage current iin - - 10 a
asahi kasei [AK5381] ms0200-e-01 2004/04 - 8 - switching characteristics (fs=4khz 48khz) (ta= ? 40 85 c; va=4.5 5.5v; vd=2.7 5.5v; c l =20pf) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 1.024 0.4/fclk 0.4/fclk 36.864 mhz ns ns lrck frequency fs 4 48 khz duty cycle slave mode master mode 45 50 55 % % audio interface timing slave mode sclk period sclk pulse width low pulse width high lrck edge to sclk ? ? (note 9) sclk ? ? to lrck edge (note 9) lrck to sdto (msb) (except i 2 s mode) sclk ? ? to sdto tsck tsckl tsckh tlrsh tshlr tlrs tssd 160 65 65 30 30 35 35 ns ns ns ns ns ns ns master mode sclk frequency sclk duty sclk ? ? to lrck sclk ? ? to sdto fsck dsck tmslr tssd ? 20 64fs 50 20 35 hz % ns ns reset timing pdn pulse width (note 10) pdn ? ? to sdto valid at slave mode (note 11) pdn ? ? to sdto valid at master mode (note 11) tpd tpdv tpdv 150 4132 4129 ns 1/fs 1/fs note 9. sclk rising edge must not occur at the same time as lrck edge. note 10. the AK5381 can be reset by bringing the pdn pin = ?l?. note 11. this cycle is the number of lrck rising edges from the pdn pin = ?h?.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 9 - switching characteristics (fs=48khz 96khz) (ta= ? 40 85 c; va=4.5 5.5v; vd=3.0 5.5v; c l =20pf; cmos level mode only) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 12.288 0.4/fclk 0.4/fclk 36.864 mhz ns ns lrck frequency fs 48 96 khz duty cycle slave mode master mode 45 50 55 % % audio interface timing slave mode sclk period sclk pulse width low pulse width high lrck edge to sclk ? ? (note 9) sclk ? ? to lrck edge (note 9) lrck to sdto (msb) (except i 2 s mode) sclk ? ? to sdto tsck tsckl tsckh tlrsh tshlr tlrs tssd 160 65 65 30 30 35 35 ns ns ns ns ns ns ns master mode sclk frequency sclk duty sclk ? ? to lrck sclk ? ? to sdto fsck dsck tmslr tssd ? 20 64fs 50 20 35 hz % ns ns reset timing pdn pulse width (note 10) pdn ? ? to sdto valid at slave mode (note 11) pdn ? ? to sdto valid at master mode (note 11) tpd tpdv tpdv 150 4132 4129 ns 1/fs 1/fs note 9. sclk rising edge must not occur at the same time as lrck edge. note 10. the AK5381 can be reset by bringing the pdn pin = ?l?. note 11. this cycle is the number of lrck rising edges from the pdn pin = ?h?.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 10 - ? timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tsck sclk tsckh tsckl vih vil clock timing lrck vih vil tshlr sclk vih vil tlrs sdto 50%vd tlrsh tssd audio interface timing (slave mode)
asahi kasei [AK5381] ms0200-e-01 2004/04 - 11 - lrck sclk 50%vd sdto 50%vd tssd tmslr dsck 50%vd audio interface timing (master mode) tpd pdn vil pdn vih vil tpdv sdto 50%vd power down & reset timing
asahi kasei [AK5381] ms0200-e-01 2004/04 - 12 - operation overview ? system clock mclk (256fs/384fs/512fs), sclk and lrck (fs) clocks are re quired in slave mode. the lrck clock input must be synchronized with mclk, however the phase is not critical. table 1 shows the relationship of typical sampling frequency and the system clock frequency. mclk frequency, sclk frequency, hpf (on or off), the input level (cmos or ttl) and master/slave are selected by cks2-0 pins as shown in table 2. all external clocks (mclk, sclk and lrck) must be present unless pdn pin = ?l?. if these clocks are not provided, the AK5381 may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the AK5381 in power-down mode (pdn pin = ?l?). in master mode, the master clock (mclk) must be provided unless pdn pin = ?l?. mclk fs 256fs 384fs 512fs 768fs 32khz 8.192mhz 12.288mhz 16.384mhz 24.576mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 48khz 12.288mhz 18.432mhz 24.576mhz 36.864mhz 96khz 24.576mhz 36.864mhz n/a n/a table 1. system clock example cks2 cks1 cks0 input level hpf master/slave mclk sclk l l l cmos on slave 256/384fs ( 96khz) 512/768fs ( 48khz) 48fs or 32fs l l h cmos off slave 256/384fs ( 96khz) 512/768fs ( 48khz) 48fs or 32fs l h l cmos on master 256fs ( 96khz) 64fs l h h cmos on master 512fs ( 48khz) 64fs h l l ttl* on slave 256fs/384/512/768fs ( 48khz) 48fs or 32fs h l h reserved h h l cmos on master 384fs ( 96khz) 64fs h h h cmos on master 768fs ( 48khz) 64fs table 2. mode select note: sdto outputs 16bit data at sclk=32fs. note: the AK5381 does not support ttl interface at 96khz. ? audio interface format two kinds of data formats can be chosen with the dif pin (tab le 3). in both modes, the serial data is in msb first, 2?s compliment format. the sdto is clocked out on the falling edge of sclk. the audio interface supports both master and slave modes. in master mode, sclk and lrck are output with the sclk frequency fixed to 64fs and the lrck frequency fixed to 1fs. mode dif pin sdto lrck sclk figure 0 l 24bit, msb justified h/l 48fs or 32fs figure 1 1 h 24bit, i 2 s compatible l/h 48fs or 32fs figure 2 table 3. audio interface format
asahi kasei [AK5381] ms0200-e-01 2004/04 - 13 - lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 20 21 24 31 0 12 23 22 0 1 0 23 22 20 21 31 23:msb, 0:lsb lch data rch data 24 321 22 23 23 1 2 3 4 figure 1. mode 0 timing lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 25 21 24 0 12 23 22 0 1 0 22 25 21 24 321 22 23 23 1 2 3 4 3 23:msb, 0:lsb lch data rch data figure 2. mode 1 timing ? digital high pass filter the adc has a digital high pass filter for dc offset ca ncellation. the cut-off frequency of the hpf is 1.0hz (@fs=48khz) and scales with sampling rate (fs). hpf is controlled by cks2-0 pins (table 2). if hpf setti ng (on/off) is changed at operating, click noise occurs by changing dc offset. it is recommended that hpf setting is changed at pdn pin = ?l?.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 14 - ? power down the AK5381 is placed in the power-down mode by bringing pdn pin ?l? and the digital filter is also reset at the same time. this reset should always be done after power-up. in the power-down mode, the vcom are agnd level. an analog initialization cycle starts after exiting the power-down mode . therefore, the output data sdto becomes available after 4129 cycles of lrck clock in master mode or 4132 cycles of lrck clock in slave mode. during initialization, the adc digital data outputs of both channels are forced to a 2?s complement ?0?. the adc outputs settle in the data corresponding to the input signals after the end of initialization (settling approximately takes the group delay time). normal operation internal state pdn power-down initialize normal operation (1) idle noise gd gd ?0?data a /d in (analog) a /d out (digital) clock in mclk,lrck,sclk (2) (3) (4) ?0?data idle noise notes: (1) 4132/fs in slave mode and 4129/fs in master mode. (2) digital output corresponding to analog input has the group delay (gd). (3) a/d output is ?0? data at the power-down state. (4) when the external clocks (mclk, sclk, lrck ) are stopped, the AK5381 should be in the power-down state. figure 3. power-down/up sequence example ? system reset the AK5381 should be reset once by bringing pdn pin ?l? after power-up. the internal timing starts clocking by the rising edge (falling edge at mode1) of lrck after exiting from reset and power down state by mclk.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 15 - system design figure 4 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. AK5381 8 7 6 3 2 1 9 10 11 12 13 14 15 16 ainl vcom agnd dgnd ainr sdto lrck mclk sclk pdn + 0.1u cks1 va vd analog 5v dif cks2 cks0 10u 10u 0.1u reset 5 4 audio controller mode control + 2.2u 0.1u + 10u 10u + + analog ground system ground lch in rch in note: - agnd and dgnd of the AK5381 should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - all input pins except pull-down pin should not be left floating. - the cks1 pin should be connected va or agnd. figure 4. typical connection diagram analog ground digital ground system controller a inr 1 a inl 2 cks1 3 vcom 4 a gnd 5 v a 6 vd 7 dgnd 8 16 15 14 13 12 11 10 9 cks0 cks2 dif pdn sclk mclk lrck sdto AK5381 figure 5. ground layout note: - agnd and dgnd must be connected to the same analog ground plane.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 16 - 1. grounding and power supply decoupling the AK5381 requires careful attention to power supply an d grounding arrangements. va and vd are usually supplied from the analog supply in the system. alternatively if va and vd are supplied separately, the power up sequence is not critical. agnd and dgnd of the AK5381 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK5381 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference the voltage input to va sets the analog input range. vcom are 50%va and normally connected to agnd with a 0.1 f ceramic capacitor. an electrolytic capacitor 2.2 f parallel with a 0.1 f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from these pins. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the AK5381. 3. analog inputs the adc inputs are single-ended and internally biased to the common voltage (50%va) with 15k ? (typ) resistance. the input signal range scales with the supply voltage and nominally 0.6xva vpp(typ). the adc output data format is 2?s complement. the dc offset is removed by the internal hpf. the AK5381 samples the analog inputs at 64fs. the digital filter rejects noise above the stop ba nd except for multiples of 64fs. the AK5381 includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs.
asahi kasei [AK5381] ms0200-e-01 2004/04 - 17 - package 0.1 0.1 0 detail a seating plane 0.10 0.17 0.1 0.65 5.0 1.10max a 1 8 9 16 16 p in tssop ( unit: mm ) 4.4 6.4 0.2 0.5 0.2 ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK5381] ms0200-e-01 2004/04 - 18 - marking akm 5381vt xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 5381vt revision history date (yy/mm/dd) revision reason page contents 03/01/24 00 first edition added explanation p.4 absolute ma ximum ratings analog input voltage (ainl, ainr pins) analog input voltage (ainl, ainr, cks1 pins) digital input voltage (all digital input pins) digital input voltage (all digital input pins except cks1 pin) 04/04/19 01 error correct p.7 dc characteristics (cmos level mode) high-level output voltage (iout= ? 20 a) high-level output voltage (iout= ? 100 a) low-level output voltage (iout=20 a) low-level output voltage (iout=100 a)
asahi kasei [AK5381] ms0200-e-01 2004/04 - 19 - important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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